<div id="readability-page-1"><div>//php echo do_shortcode('[responsivevoice_button voice=&#34;US English Male&#34; buttontext=&#34;Listen to Post&#34;]') ?&gt; As AI models become a key driver of global competitiveness and AI hardware used for training and inference is increasingly treated as a strategic asset rather than a commodity, developing sovereign AI platforms has gained importance as a way to reduce reliance on foreign suppliers. Europe, still a relatively small player in chip design and systems, lacks a homegrown AI hardware stack, unlike the U.S. and China. That gap may begin to narrow as SiPearl and Semidynamics this month announced a partnership to build one of the first European sovereign rack-scale AI platforms.<h3>SiPearl-Semidynamics AI platform: hardware</h3>The sovereign AI platform jointly developed by SiPearl and Semidynamics is a multi-generation, multi-year effort aimed at developing a competitive European rack-scale AI platform based on technologies from both companies.The platform will rely on SiPearl’s Arm Neoverse V2-based Rhea2, and subsequent generations of processors, to handle general-purpose and orchestration tasks, alongside Semidynamics’ RISC-V-based AI inference accelerators (which the company describes as GPU/AI inference ASICs) serving as the main compute engines. SiPearl CEO Philippe Notton told EE Times that Rhea2 is still ‘in design’ and that development is expected to move significantly faster than Rhea1, as the company now has a mature engineering team, established design flows, and experience developing complex HPC processors. Yet, unlike Rhea1, Rhea2 will lack a complex memory subsystem featuring onboard HBM for bandwidth-hungry HPC applications (e.g., fluid dynamics compute) and another DDR5 memory pool for capacity-heavy workloads. Rhea2 will only rely on a DDR-type memory, which will simplify memory coherence with AI accelerators. The accelerators will use Semidynamics’ existing IP with refinements, drawing on architectures derived from the company’s current Cervell NPUs with on-chip memory. “[The accelerators] are based on our previous IP developments, with refinements,” David Harold, CMO of Semidynamics, told EE Times. “It is closer to a programmable AI inference accelerator than to a conventional graphics GPU. We use GPU [term] in the data center AI sense: a device that performs the heavy AI compute in the rack. The architecture combines RISC-V CPU control, vector, and tensor capability, and a differentiated memory subsystem. The aim is to support large-scale inference workloads, including large models and long contexts, without locking customers into a narrowly fixed-function accelerator.”While the first-generation platform will combine SiPearl’s Rhea2 CPUs and Semidynamics’ RISC-V accelerators, later generations are expected to pursue further integrations at the chiplet level, echoing data center-grade heterogeneous multi-chiplet designs, such as AMD’s Instinct MI300A. However, given architectural differences between Semidynamics’ architecture and AMD’s approach, the result will be completely different.“The second iteration is intended to move toward tighter chiplet-level integration, but we would not describe it as equivalent to a specific existing architecture such as AMD’s MI300A,” Harold said. “Semidynamics is using a chiplet-based approach rather than a giant monolithic die, and chip-to-chip connectivity uses UCIe. Certainly, tighter integration with SiPearl’s silicon is possible and is being contemplated. The broader memory model and package-level details will be disclosed later.”Notton continued, “A challenge we face in Europe, and we want to be a significant player, is to ensure that our chiplets will work with [other] chiplets, which will be accelerator chiplets coming from Semidynamics or others. With Rhea2, you have a UCI interface, so it can work with various accelerators.”One of the challenges with accelerator architectures that feature on-chip memory is enabling memory with CPUs. Such designs are optimized to keep data local to maximize bandwidth efficiency and minimize latency, whereas coherence requires constant synchronization, cache tracking, and remote visibility across CPUs and accelerators. Hence, coherence can simplify programming but also erodes some of the benefits of such architectures, since coherence traffic increases power consumption, latency, area overhead, and verification complexity. From our conversation with Notton, one of the key points is that the first-generation platform is expected to support full CPU-accelerator memory coherence. Notton explicitly confirmed this and suggested the same direction applies to later generations as well.“This is part of the work we will be doing with SiPearl in the near future,” Harold said.Truth to be told, even advanced heterogeneous systems from AMD and Nvidia typically use hybrid coherence models, where only certain memory regions are kept coherent while many local accelerator memories remain outside coherent domains. At this point, it is hard to tell how SiPearl and Semidynamics plan to enable coherence.For now, Semidynamics is not disclosing the RISC-V instructions and data formats supported by its upcoming AI accelerators, though the company says the processors will be programmable using industry-standard tools such as Linux, GCC, and LLVM, rather than relying on a closed proprietary software ecosystem.“We are not yet disclosing the full instruction and data-format support,” Harold said. “At the architectural level, the point of using RISC-V is to preserve openness and programmability. The system is designed to work with standard software infrastructure such as Linux, GCC, and LLVM, rather than requiring customers to adopt a closed proprietary programming environment. We will disclose more on specific instructions and data formats closer to product introduction.”The design will follow Open Compute Project (OCP) specifications to ensure compatibility with established cloud and data center ecosystems, as well as already available hardware. This approach is intended to speed up time to market and benefit from economies of scale across widely deployed components, ranging from solid-state drives to server racks, and from motherboard components to power supplies.“Our intent is to reduce deployment friction by aligning with data center infrastructure practices and familiar software environments,” Harold said. “We are designing the platform for rack-scale deployment by operators and integrators, rather than as a standalone chip that requires customers to build everything around it. We will provide more detail on the specific OCP-compatible elements as the system design is disclosed.”<h3>Rack-scale approach</h3>In line with broader industry trends, SiPearl and Semidynamics are developing rack-scale platforms rather than just a CPU and just an accelerator that are meant to work together. Specifically, the companies expect the platform to offer ‘excellent performance‑per‑watt’ as well as to offer ‘density on par with leading AI platforms.’ Both statements are intentionally vague and avoid specific numbers, though the general message about building an efficient and competitive rack-scale platform is clear. “We are targeting data center rack-scale AI inference, not an edge or low-power-only PCIe product,” Harold said. “The roadmap includes a PCIe card for developers and early system work and extends to liquid-cooled data center rack solutions.”The reference to liquid-cooled racks clearly points to a platform resembling those developed by Nvidia—and AMD—where an entire rack packs dozens of accelerators connected in scale-up configuration and functioning like a single accelerator. So, when Semidynamics and SiPearl mention density expected from leading global AI platforms, they almost certainly mean very high accelerator counts per rack. Yet, the claim about similar density does not necessarily transform into similar performance density.“We are not yet disclosing the number of accelerators per rack, so it would be premature to map the design directly onto 72- or 144-accelerator configurations,” Harold said.Rack-scale interconnection technologies, such as Nvidia’s NVLink, and their topology are key to unlocking the scalability of AI accelerators. While the interconnection fabric for the Semidynamics accelerators is certainly a thing that the two companies are working on, for now, they are not ready to discuss details about the technology.“We are not disclosing the full rack-level fabric yet,” Harold said. “Semidynamics has developed a scale-up approach for connecting accelerators within the rack, and the chiplet-level connectivity uses UCIe. We will provide more detail on the CPU-accelerator interconnect and rack-level fabric as the platform moves closer to market.”In any case, both next-generation SiPearl CPUs and the multi-chiplet-based AI solutions jointly developed by SiPearl and Semidynamics will use UCIe interconnects.“For the next generations [of CPUs], we are moving to chiplet,” Notton said. “In fact, that is what big players [such as] Intel, AMD, and Nvidia are doing. We do not have any choice because it becomes quite [hard] to develop large dies. So we have to fragment the design. […] Once we have chiplets, it is mix and match. You can combo other stuff together.”Notton also highlighted one of the industry’s biggest unresolved problems: ensuring reliable interoperability between chiplets from different vendors. He noted that current chiplet ecosystems from companies such as Intel, AMD, and Samsung Electronics remain largely vertically integrated, underscoring the importance of close collaboration between SiPearl and Semidynamics to ensure their multi-chiplet AI platform operates reliably.Notton also explicitly confirmed that the platform will require a scale-up fabric conceptually similar to NVLink, though he declined to disclose implementation details. When asked directly about rack-scale fabrics, he acknowledged the importance of stitching the system together but said the topic is at an early stage.“You still need to stitch all of them, all of those things together,” Notton said. “To stitch all of the things together, you need a scale-up fabric like NVLink, [but] we do not comment yet. […] It is quite early stage and sensitive.”<h3>Software</h3>A software ecosystem tailored for AI workloads is one of the primary reasons Nvidia remains the leading supplier of AI hardware. To compete not only with Nvidia, but with a host of other suppliers, SiPearl and Semidynamics need to ensure that their software stack is both accessible and flexible. The good news is that Arm-based CPUs for AI systems and RISC-V-based AI accelerators have already made it to the market and are already supported by a broad software ecosystem.“The platform is intended to integrate with existing AI data center software environments rather than require customers to adopt a closed proprietary stack,” Harold said.“Semidynamics expects the racks to support vLLM, SGL, ONNX, and PyTorch when they ship,” he added. “At the lower level, the company is emphasizing Linux, GCC, and LLVM support, using RISC-V openness to make the platform programmable and accessible to a broad software ecosystem. There will, of course, be Semidynamics software at the lower layers where PyTorch operators are dispatched to the accelerator, but the intent is to publish and open that layer rather than treat it as a closed CUDA-like island.”<h3>Positioning</h3>SiPearl and Semidynamics position their upcoming platform for public and private AI data center deployments. Specifically, they mention both enterprise-scale inference as well as large-scale AI clusters used to run performance-hungry large language models (LLMs) and retrieval‑augmented generation (RAG) workloads. “The first-generation platform is focused on large-scale inference,” Harold said. “That includes LLM serving, large models, long-context workloads, and emerging workloads that require much larger context windows and datasets. We see inference moving beyond simple single-prompt LLM serving toward more demanding reasoning and multimodal use cases, including video and long-context processing. We are not making a separate product claim around agentic AI at this stage, but we note agentic AI puts additional stress on the memory capacity of AI agents, and the architecture is intended to support the direction inference and agentic workloads are moving.”Speaking about agentic AI workloads, SiPearl’s CEO also suggested the industry is moving away from the traditional 1:8 CPU-to-GPU ratio toward something closer to 1:2 for many inference deployments. He also noted that agentic AI could drive demand for CPU-heavy or even pure CPU racks, which is something that executives from both Intel and Nvidia envision.“What we see is [that] the CPU-to-GPU ratio is changing,” Notton said. “It was 1:8 in the past, […] 1:2 is a good target. […] For agentic AI, [we] even got requests of only CPUs, pure rack of CPUs.”To address CPU-heavy workloads, the rack-scale solution will support the option of CPU-only racks, Notton said. Meanwhile, he stressed that the two companies are developing a reference design for partners—who have not yet been disclosed—to manufacture that their partners (which are not disclosed at this time) will produce, rather than selling complete racks themselves, unlike Nvidia. Still, Notton acknowledged that modern CPU vendors increasingly need to engage in rack-level design to ensure competitive time-to-market and appropriate system integration.“The key is to ensure that we have a rack which is modular,” Notton told EE Times. “So, depending on the request, we can change the configuration. […] It is clear that we need ODMs to help us in building these kinds of platforms because we do not have any intention to ship and to design our own rack.”Since the two companies are developing an AI platform that is aimed primarily at inference, their general focus is maximum efficiency, programmability, and low total cost of ownership rather than ultimate performance.“We are not trying to win only on peak compute numbers,” Harold said. “We are designing for efficient token generation in real data center deployments. That means memory efficiency, programmability, system integration, and cost structure are as important as raw throughput. It is also why we are not dictating the use of HBM in the current design. HBM creates supply and cost challenges, and we believe there is value in a fundamentally different cost structure for inference systems.”The companies’ reference to OCP compatibility suggests scalability from traditional enterprise deployments to hyperscale-class power infrastructure, although the latter is not mentioned specifically. Furthermore, both companies participate in the European Processor Initiative (EPI), EuroHPC, and some other government-led initiatives, so expect them to address government-backed infrastructure first, then move on to enterprises, and then approach hyperscalers. Still, the actual business plan is something that remains to be seen.The platform also targets various European initiatives, such as AI Factory and Giga Factory programs, which favor domestic architectures and localized supply chains. Still, the companies acknowledge that the chips powering the platform will not be manufactured in Europe.“Our aim is to give European AI infrastructure providers a credible European-led alternative for large-scale inference,” Harold explained. “That does not mean every element of the semiconductor supply chain is physically located in Europe. Advanced semiconductor manufacturing remains global. But Semidynamics brings European control over crucial architecture, system design, software direction, and commercial deployment, which are critical parts of sovereignty in AI infrastructure.”On sovereignty, Notton offered unusually candid remarks about Europe’s semiconductor limitations. He said that for security reasons, design infrastructure, compute farms, and even emulation systems are kept in Europe, while advanced manufacturing and packaging remain dependent on Taiwan for now.“What we do is design in Europe,” Notton said. “The compute farm to manage the design is in Europe and is European. In fact, it is our own compute farm. Our emulation capacity is in Europe, and we own it. […] Everything is done out of [the] U.S. cloud for safety reasons. Today, for generation 1 and generation 2, foundry packaging is in Asia. It is in Taiwan. No choice.”He also identified advanced packaging as a potential first step toward restoring parts of semiconductor manufacturing capacity in Europe, citing Singapore-based Silicon Box and its Italian expansion in 2024.“Advanced packaging may be the first one to arrive in Europe,” Notton said. “One of the good examples is Silicon Box in Italy. This company from Singapore has set up a base camp in Italy. It is maybe the first step to have some part of the fab in Europe.”<h3>Availability</h3>On availability, there is no firm launch timeline. Before introducing the Rhea2 CPU, SiPearl must first bring the Rhea1 processor to market; it is currently in sampling. As a result, the first-generation SiPearl-Semidynamics AI platform is likely still a few years away.As for Semidynamics, the company has already completed a 3-nm test chip for architectural validation and customer evaluation, with a production design tape-out scheduled for later this year.“We have completed a successful 3-nm test chip, which provides a platform for architectural validation and customer analysis,” Harold said. “A production tape-out is planned for later this year, followed by system bring-up. The next major milestones are production tape-out, silicon bring-up, system integration, and then customer deployment. We will be more specific on availability once those milestones are further advanced.”Philippe Notton confirmed that the jointly developed SiPearl-Semidynamics AI platform is intended to arrive ‘this decade,’ not the next one. The final version of Rhea2 is scheduled to tape out in 2027, when hardware and software developers will begin system integration. He also stressed that SiPearl intends to dramatically shorten development cycles compared to Rhea1 and ultimately match the execution pace of major U.S. companies.“It has to be this decade, that is why we need to act fast,” Notton said. “Rhea2 will tape out in 2027, let us say for the advanced version, but there is some other stuff that will happen before. […] Generation 1 took a while to be done because we had to build the company, we had to find the money. From generation 2 and generation 3, we definitely need to reduce the design cycles. [It] cannot take five years to design a processor. […] We need to be faster. Now the team is mature, we know what to do.”<hr/><h5>Read also:</h5><hr/> AI ACCELERATOR, AI INFERENCE, AI MODELS, ARM, DATA CENTER, PROCESSORS, RISC-V, SEMICONDUCTORS, SOVEREIGN AI ARM, RISC-V INTERNATIONAL, SEMIDYNAMICS, SIPEARL S.A. </div></div>

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SiPearl and Semidynamics have announced a partnership to develop a European sovereign AI platform, utilizing SiPearl's Arm Neoverse V2-based Rhea2 processors and Semidynamics' RISC-V-based AI inference accelerators. This multi-year project aims to create a competitive rack-scale AI platform, addressing Europe's need for a homegrown AI hardware stack. The first generation will focus on CPU-accelerator memory coherence, with future iterations expected to enhance chiplet-level integration.

- SiPearl and Semidynamics are collaborating to develop a European sovereign AI platform aimed at reducing reliance on foreign suppliers.  
- The platform will utilize SiPearl’s Rhea2 processors and Semidynamics’ RISC-V-based AI accelerators for efficient AI inference, with future generations planned for tighter chiplet integration.  
- While advanced manufacturing remains reliant on Asia, the initiative aims to provide a credible European alternative for large-scale AI data center deployments, although no firm launch timeline has been set.

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When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform