How the memory race ultimately ends comes down to one question: will AI be more constrained by capacity or by bandwidth?

That single variable drives three scenarios.

1) Capacity-bound: parameter counts stop exploding, and demand is driven by more users and longer context windows.

Back-end memory, standard DDR, and HBF can fill the gap.

Memory reverts to a commodity game focused on capacity and cost — but it is also the most 'cyclical', and once supply ramps, pricing comes under the most pressure.

2) Bandwidth-bound: parameter counts keep climbing and speed requirements rise.

The focus of competition shifts from 'stacking memory' to packaging and substrate/process technology, with bargaining power spilling over to foundries like TSMC.

Memory vendors start to look more like 'die suppliers'.

3) Both in short supply: the industry enters a memory 'super-cycle'.

All paths are pursued in parallel, DRAM wafer and advanced packaging capacity both run tight.

Memory makers carry the most weight in this setup.

In practice, all three will likely coexist; the difference is which one dominates.

Watch a few signals: the layer and stack counts of new HBM, realized speeds for HBM4E, the relative capacity ramp between CoWoS and DRAM wafers, and first-wave adoption of HBF.