MU (Analyst huddle): SCA covers 35% of revenue; at least two nodes ahead of Chinese peers

Below is Dolphin Research’s transcript of Micron Technology’s FY26 Q4 post-earnings analyst call. For the earnings take, see ‘Micron: With the frenzy over, can LT contracts carry memory’s rebirth?’

I. $Micron Tech(MU.US) Key takeaways from the print

1. FQ1 modeling: Guidance assumes low-single-digit QoQ bit shipments for both DRAM and NAND, with double-digit moves in cost.

2. FY27 R&D raised: Ex-stock comp, FY27 R&D will be up by more than the prior guide’s $1bn YoY. With new programs added, FY27 R&D YoY increase will exceed $1bn.

3. FY27 GPM trajectory reaffirmed: After FQ1, gross margin is expected to expand each quarter through the year, driven by further price increases (at a more measured pace) and mix uplift from technology and product leadership. Start-up costs for new fabs will partially offset. Management expects a tight market to persist into 2028, supporting strong financial performance.

4. CapEx mix: The incremental FY27 CapEx vs. prior plan is mostly construction CapEx, largely to accelerate cleanroom availability by end-2028 and beyond. This trend likely extends past FY27. Construction spend itself does not directly translate into bits; equipment will be installed later based on demand. The company has LTAs with tool vendors to ensure availability when needed.

5. China exposure: Revenue exposure to China has steadily declined over the past few years and recent quarters, and is expected to fall to single digits in FY27.

II. Call details

2.1 Management highlights

1. Strategic Customer Agreements (SCA) — new disclosures

a. 26 SCAs cover about 35% of sales through 2030 across both DRAM and NAND. On a bit basis, DRAM is slightly below ~35%, NAND slightly above that level (explicitly clarified as bit-based shares).

b. Of the 10 SCAs signed this quarter, customer sizes range from small to large. Micron now has SCAs across all BUs (including the Mobile & Client BU, MCBU) to keep diversified end-market coverage, but does not break them out.

c. SCA structures are broadly unchanged, with most priced deals using floor/ceiling bands. New SCAs were negotiated off today’s market and anticipated tightness, pointing to higher pricing, while earlier ones reflected 2Q market conditions. About 3/4 of SCA revenue has explicit pricing frameworks, ~1/4 is periodically renegotiated off market dynamics. Multiple frameworks are in use, and management did not disclose whether hyperscalers are included.

2. HBM and advanced products

a. No update to HBM TAM, but the view stands: HBM shipments will grow faster than conventional DRAM, lifting HBM’s share of industry capacity through 2028. 2027 calendar-year HBM pricing has been raised materially and will reset at the start of the year, narrowing the profitability gap vs. conventional DRAM.

b. HBM share: roughly a year ago Micron reached the milestone where its HBM share matched its broader DRAM share. Thereafter, no single-share target is set, but HBM share is expected to hover around overall DRAM share, with fluctuations.

c. HBM4E / NVHBM: Micron has worked with Nvidia for over a year on what will be the market’s first major customized HBM product. Key clarification: HBM4 uses a Micron-designed base die, whereas HBM4E (NVHBM) is co-designed on foundry process for both custom and standard versions. Differentiation lies in power, max speed, and yield margins. Vendors have varied across HBM generations on these vectors; Micron views this as a continued quality and capability edge. HBM is a premium category, and customized NVHBM is also expected to deliver high value and ROI.

3. Tech roadmap and China competition

a. Micron believes it is at least two nodes ahead of Chinese competitors, with strategy centered on maintaining leadership and real product differentiation.

b. 1-gamma DRAM already accounts for the majority of Micron’s bits and will be the largest node in company history, relying on EUV. Next-gen 1-delta is progressing well and targets ramp in 2H next year. EUV is critical for all future advanced DRAM nodes; Micron’s EUV expertise, supplier partnerships, and mask technology remain key differentiators.

c. On wafer-level DRAM fungibility: management argues the opposite of interchangeability — FEOL process optimizations for HBM, high-performance SOCAMM, LP DRAM, and DDR now differ more than ever. Product differentiation at the same node is unprecedented. The true value of fungibility is running multiple products on the same line to flex mix in line with demand, not cost reduction.

4. New demand vectors: CPU and agentic workloads

a. Management sees ‘agentic workloads on CPUs’ as the biggest incremental change YTD. These workloads have high attach for LP/DDR memory and SSDs, helping drive server unit growth in the high-teens.

b. This trend lifts logic consumption and AI compute demand, further tightening DRAM. Management explicitly stated DRAM is the primary bottleneck, not logic or data center power.

c. Multiple agent software deployments are live in enterprise and consumer, creating real value.

5. Structural supply constraints

a. Node-migration bit gains are diminishing vs. history. HBM’s faster growth through 2028 raises its share of industry capacity. As HBM moves from 3E to 4 to 4E in late 2027, trade ratios rise, and more complex HBM will carry even higher trade ratios.

b. Cleanroom space is the industry’s primary constraint: build, qualification, and tool installs take a long time. Even with Micron’s Idaho fab producing first wafers by mid-2027 and peers bringing cleanrooms online, meaningful bit output comes several quarters later.

c. On NAND, Micron’s supply growth lags industry this year partly because some Singapore cleanroom space is used for advanced R&D lines for future NAND, and to prep for next year’s Singapore HBM ramp. Management is confident that G9’s ramp brings high-ROI, low-cost supply. The new Singapore NAND cleanroom goes online in 2H 2028.

6. Policy and industry context

a. Micron was invited to a U.S. Gov. AI forum alongside model and accelerator companies, underscoring memory’s importance.

b. The resulting white paper framework, signed by multiple model companies, is constructive for sustained AI infra, especially AI hardware infra.

c. A key theme: address safety via building safety solutions, which require more advanced hardware — higher-performance, lower-latency, higher-bandwidth memory. Future gateways managing safety will depend heavily on the availability of high-performance, low-latency memory.

2.2 Q&A

Q: You now say 2028 looks tighter than 2026/2027. What changed? What does this imply for 2028 margins, and why below the implied 2027 level?

A: For 2027 and 2028, we see stronger demand drivers than before. Server units continue to grow in 2027, and agentic AI is scaling fast, creating a CPU-driven demand stream. As we advanced FY27 planning, we noted over 75% of full-year shipments are already allocated, signaling strengthening demand and pushing allocation discussions with customers into 2028. That underpins our confidence — 2027 demand is stronger than previously seen. We also have more SCA discussions, including extensions, boosting our long-term confidence. Together, these support a very strong demand outlook through 2028.

On supply, the structural constraints we’ve discussed remain: diminishing node-migration gains, HBM growing faster than conventional DRAM and taking a larger share of industry output, and rising trade ratios — not just today’s HBM, but even higher with more complex HBM. Meanwhile, new cleanrooms take a long time from build to qualification to tool install; even post-opening, meaningful shipments take several quarters. The combination leads us to say we don’t see when supply and demand balance.

To add: for 2027, we expect margins to expand through the year vs. Q1, driven by continued price increases, though at a slower pace. We’ve long said price hikes would moderate; at that stage, alongside slower price gains, we benefit from better mix, leaning on tech and product leadership. As noted, the market should stay tight into 2028, supporting results. Start-up costs partially offset price and mix, but these are manageable, and we expect to sustain strong performance.

Q: Sanjay attended the White House AI forum. What did you take away on growth and self-regulation? Was memory a key topic?

A: Sanjay isn’t here today, but a few notes: we were delighted to participate. Being invited alongside model and accelerator companies highlights memory’s importance. The forum’s white paper framework, already signed by many model players, is constructive for advancing AI infrastructure, especially hardware. A concept discussed heavily: to manage safety, build safety solutions, which require more advanced hardware — higher performance, lower latency, higher bandwidth memory. Many safety mechanisms will be deployed as gateways whose responsiveness will hinge on high-performance, low-latency memory.

Q: You’ve given HBM TAM views for 2028/2030, but pricing has changed. Any update? How much of the delta is bits vs. price?

A: No TAM update today. Our stance remains that HBM shipments will outgrow conventional DRAM, lifting its share of industry capacity by 2028. On pricing, for us, 2027 calendar-year HBM prices have been materially raised and will reset at the year’s start, narrowing the profitability gap vs. conventional DRAM. Beyond that, no further TAM specifics. The market keeps expanding, HBM is a critical enabler, and its deployment is essential for the rest of the stack to realize potential.

Q: Is your HBM share target still to match overall DRAM share (low-20%s)? And any update on 2027 HBM4E and the Nvidia collaboration?

A: About a year ago, we reached the milestone of HBM share matching our broader DRAM share. Since then, we haven’t set a fixed target — we expect HBM share to hover around overall DRAM share, with variability. As noted, HBM is strategically important, keeping us on the leading edge of customers’ accelerator platforms and enabling AI to deliver on its promise.

On Nvidia, this will be the first major customized HBM in the market. We’ve co-developed HBM4E (NV HBM) with Nvidia for over a year. The opportunity is to co-design with a key customer to deliver value well above standard HBM4E. We think it will be impactful for the industry and showcase the direction of future system-level optimization.

Q: The 26 SCAs covering ~35% of sales through 2030 — does that include both DRAM and NAND? Any split?

A: We won’t split it, but SCAs do cover both DRAM and NAND, running through 2030. What we can say is DRAM bits are slightly below ~35%, NAND bits slightly above. As we progress SCA discussions, this share can rise further. To clarify, those DRAM/NAND shares refer to a bit basis.

Q: Can you confirm China sales exposure is now quite small? And Scott, how fast are Chinese competitors catching up technically?

A: On exposure, our China revenue has been declining over the last few years and recent quarters. We expect FY27 to be in the single digits. On technology, we are at least two nodes ahead of Chinese peers. Our focus is to maintain leadership and compete with genuine product differentiation. As noted, our 1-gamma DRAM already represents the majority of our bits and will be our largest node, leveraging EUV. 1-delta is on track, with a focus on ramping in the back half of next year. EUV is critical for all advanced DRAM nodes, and our know-how — including supplier collaboration and mask technology — remains a key differentiator.

Q: Mobile and Client posted a second straight quarter of bit shipment declines. Are higher memory prices suppressing demand? And has SCA adoption improved in these segments?

A: Mobile did see QoQ bit declines, but revenue still grew on higher pricing and favorable mix. Demand for higher-capacity, higher-performance solutions remains strong in client and premium smartphones, which we focus on. With such tailwinds, even with unit softness, both PC and smartphone revenue are growing. On SCAs, we have SCAs across all BUs, including Mobile & Client, to maintain diversified end-market supply, though we don’t break them out.

Q: How competitive is your optimized in-house base die on HBM4E? Do complexity and economics accrue more to compute customers or HBM suppliers?

A: Clarification: for HBM4E, we co-design with Nvidia, but we do not use our own base die as we do on HBM4. HBM4E is co-designed on foundry nodes for both custom and standard products. As with prior HBM generations, differentiation ultimately shows up in power, max speed, and margins co-optimized with customers. Vendors perform differently across these, and we see this as a continued edge for Micron’s quality and delivery. On economics, HBM is a premium product. As Scott noted, customized NV HBM is also expected to be premium. We are confident HBM will remain a high-ROI contributor.

Q: For the 10 new SCAs this quarter, what were customers’ priorities? Any change in pricing mechanics — given 2027/2028 tightness, are you less willing to set fixed bands to capture more upside?

A: The framework is similar, but negotiations reflect today’s market and forward price views. The direction has been up. As disclosed, ~3/4 of SCA revenue has explicit pricing frameworks, and ~1/4 resets periodically off market dynamics. Most priced frameworks include floor/ceiling bands, but newer deals are set against current conditions and expected tightness.

Q: Does that mean all floors/ceilings were reset higher? Or did the nature of pricing terms change? Also, have you signed initial hyperscalers, and are they included?

A: We use multiple frameworks. Most priced ones have bands, but we continue to employ various structures. Among the 10 new SCAs, we signed a range from small to large customers. We don’t comment on specific customers or split by type. We’ll just note we now have SCAs across all BUs, and across both the 10 new and the total 26 SCAs, customer sizes span small to large.

Q: Can you compare construction CapEx vs. equipment? Construction is ramping faster, but won’t translate into bits until at least 2029.

A: Exactly. Cleanroom space is the primary bottleneck, as AI demand accelerated recently relative to the long build cycle for cleanrooms. Everyone is early on this, which is why we’re focused here. We did say the incremental FY27 construction CapEx vs. plan is largely for cleanrooms that come online in late-2028 and beyond. That shows how long builds take and why we must invest now, and it underscores our LT demand confidence. This confidence comes from near-term trends, SCA structures, and discussions extending customer commitments beyond 2030. SCAs are transformative, letting us align supply to future demand and invest with conviction.

To be clear, most of the incremental is construction CapEx, and most of that accelerates cleanroom availability for 2028 and beyond. We expect this to continue post-FY27. Importantly, construction spend alone doesn’t produce bits. We will tool the fabs and run wafers based on market needs, and SCAs help ensure returns on this CapEx. We will equip cleanrooms according to demand at that time. We are also signing LTAs with tool vendors to ensure availability, but installs and capacity builds will be paced by demand.

Q: How much does stronger CPU demand move the needle for bit demand and balance? CPUs don’t have an HBM-like trade ratio — how material is the impact?

A: Recognizing that ‘agentic workloads run on CPUs’ is a major driver. These workloads have high attach to LP/DDR memory and SSDs and are already ramping, with multiple enterprise and consumer deployments delivering real value. This is one reason server units can sustain high-teens growth. It’s also another channel for logic to benefit from AI, lifting logic wafer consumption and overall compute demand. Frankly, it further tightens DRAM, making it clearer that DRAM is the main bottleneck, not logic or data center power. Meta’s rapid rollout over the past two weeks illustrates how fast agentic workloads are delivering consumer value.

Q: Given your CapEx, it’s surprising supply growth slows next year. Beyond HBM’s dampening effect, what else drives slower supply growth, mainly for DRAM?

A: We’ve said HBM grows faster than conventional DRAM, and as the industry moves from HBM3E to HBM4 and to HBM4E in late 2027, trade ratios rise. Together, these suppress bit growth capacity. Also remember, for us and others, bit growth from new nodes depends on the timing of migrations and the structural diminishing returns per node generation. All of these constrain supply. But the biggest constraint remains cleanroom space. Even with Idaho’s first wafers in mid-2027 and peers opening cleanrooms, meaningful supply growth comes several quarters later. Hence our view that DRAM industry supply shipment growth will slow next year.

Q: If your supply view is conservative and actual supply is higher next year, can the market absorb it? There seems to be pent-up demand — customers down-specced out of necessity; would they simply re-up memory configs?

A: Exactly — as Sanjay noted on the main call, customers are maximizing compute silicon shipped based on available memory. That creates latent demand for more memory, which would drive higher system performance and better end-user experience. So yes, if more memory becomes available, it would be readily absorbed by AI-intensive workloads, whether attached to accelerators or CPUs.

Q: You said NAND bit growth trails industry this year. What about 2027–2028 — can you match the ~25% industry growth?

A: We don’t guide that far out for DRAM or NAND. We do expect overall NAND conditions to stay tight, even with industry growth of ~25% in 2027 and 2028. Drivers of our relative growth: some Singapore cleanroom space is allocated to advanced R&D lines for future NAND, and we are prepping for next year’s Singapore HBM ramp, using some existing cleanroom for pilot runs. Hence our below-industry growth this year. We remain confident in our technology. The ongoing G9 ramp should provide high-ROI, cost-efficient supply. And the new cleanroom we broke ground on earlier this year will come online in 2H 2028.

Q: If DRAM devices are the same at the wafer level and differences are mostly in BEOL, does this fungibility improve DRAM cost management?

A: Partly, but we’d say the reality is the opposite. FEOL process differences — optimizing DRAM for HBM, high-performance SOCAMM and LP DRAM, and DDR — are now perhaps the largest in DRAM history. The degree of product differentiation at the same node is unprecedented. Near term, yes, running different products on the same line helps mix flexibility without swapping across fabs. But each product has unique optimization: HBM for bandwidth with TSVs and distinct steps; DDR and LP with their own. Thus, the key value is flexible allocation and mix shifts within a site to meet demand. We wouldn’t say it delivers meaningful cost benefits.

(Two modeling notes added at the end)

A: Glad the focus was on technology and long-term fundamentals. Two clarifications for your models: First, our FQ1 guide assumes low-single-digit QoQ bit growth for both DRAM and NAND, with double-digit moves in cost. Second, excluding stock comp, FY27 R&D YoY increase will be above the $1bn we cited last quarter, as we have added R&D activities. We want to ensure this is captured in your models.

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